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or1-design
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OR-1 dataflow CPU sketch
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Overview
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or1-design
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docs
4 folders
·
4 files
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main
Orual
·
feat: implement frame matching lanes for concurrent PE matching
·
6mo ago
264195f0
design-plans
feat: implement frame matching lanes for concurrent PE matching
6mo ago
implementation-plans
feat: implement frame matching lanes for concurrent PE matching
6mo ago
plans
bugfixes in monitor and graph renderer, improvements to SM visibility
7mo ago
test-plans
feat: implement frame matching lanes for concurrent PE matching
6mo ago
assembler-redesign-plan.md
feat: rewrite ProcessingElement with frame-based matching, output routing, and unified instruction set
6mo ago
emulator-redesign-plan.md
feat: rewrite ProcessingElement with frame-based matching, output routing, and unified instruction set
6mo ago
macro-enhancements.md
updating docs
7mo ago
test-requirements.md
fix(asm): address code review issues — invalid port errors, @ret leak, test gaps
7mo ago
