fix: correct pipeline timing for EXTRACT_TAG, SM dispatch, ALLOC_REMOTE, FREE_FRAME master
All monadic instruction paths (normal ALU, EXTRACT_TAG, SM dispatch, ALLOC_REMOTE, FREE_FRAME) now follow the same consistent timing pattern: 1. Compute/prepare result 2. Fire Executed event 3. yield(1) for EXECUTE cycle 4. yield(1) for EMIT cycle 5. Fire output event or perform the action This ensures all monadic paths take exactly 4 cycles as per AC3.10: - dequeue(1) + IFETCH(1) + EXECUTE(1) + EMIT(1) = 4 cycles Previously, EXTRACT_TAG, SM dispatch, and ALLOC_REMOTE had the emit happening BETWEEN the two yields (3 cycles), and FREE_FRAME had timing inconsistencies. Also add 4 new timing tests for the special paths: - test_extract_tag_timing: verifies EXTRACT_TAG emits at 4 cycles - test_sm_dispatch_timing: verifies SM dispatch emits at 4 cycles - test_free_frame_timing: verifies FREE_FRAME frees frame at 4 cycles - test_alloc_remote_timing: verifies ALLOC_REMOTE executes at 2 cycles Fixes code review feedback issue: Pipeline timing inconsistency across EXECUTE paths