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OR-1 dataflow CPU sketch
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fix(asm): address code review issues — invalid port errors, @ret leak, test gaps master
- C1: Invalid port parameter values now produce MACRO errors instead of silently falling back to Port.L. _clone_and_substitute_edge returns errors like _clone_and_substitute_node already does. - I1: Leaked @ret edges from failed inner macro expansions are now filtered out to prevent spurious cascading errors at outer scope. - I2/M3: Added tests for invalid port values and bare @ret with only named outputs. - M1: Fixed test-requirements.md file references to match actual names. - M2: lower.py edge qualification now uses replace() to preserve all fields (port_explicit, ctx_override) instead of constructing new IREdge.
Author Orual Date (Mar 3, 2026, 2:43 PM UTC) Commit 734df023 734df023c6ab775f6203cd39b15a10e25ae20f38 Parent cf93d659 cf93d65958e1ec7fb326b5309c70bbdb2ad56f86 Change ID rknypkkw rknypkkwltqxmyutyuplyzokllnzylnk