feat: Phase 6 Subcomponent A - Codegen rewrite for frame-based model (Tasks 1-3) master
Task 1: Rewrite _build_iram_for_pe() to produce dict[int, Instruction] from allocated IRNodes - Replaced ALUInst/SMInst with unified Instruction type - Mode fields (output, has_const, dest_count) taken from allocate pass - Simplified implementation removes Addr construction and ctx_mode encoding Task 2: Add frame setup token generation _generate_setup_tokens() - Generates ordered token sequence: SM init → IRAM writes → ALLOC → frame slot writes - IRAM writes use PELocalWriteToken(region=0) with pack_instruction() data - ALLOC uses FrameControlToken for each activation - Updated AssemblyResult to include setup_tokens field Task 3: Update seed token generation for act_id - Seed tokens use act_id field (not ctx), no gen field - Updated generate_direct() and generate_tokens() to use new API - DyadToken/MonadToken construction simplified Tests: - New test file: tests/test_codegen_frames.py with 14 comprehensive tests - Updated tests/test_codegen.py for frame-based model compatibility - All 29 tests pass (14 new + 15 updated) Verification: - pack_instruction() correctly encodes Instruction to 16-bit words - Token ordering verified: SM init before IRAM writes before ALLOC before seeds - Seed tokens use act_id, no gen field present - ALLOC tokens generated per activation per PE