diff --git a/cdrom.jam b/cdrom.jam
index 917447b..eb1ba63 100644
--- a/cdrom.jam
+++ b/cdrom.jam
@@ -190,7 +190,7 @@ pub const Cdrom = struct {
         if (discLoaded(disc) != 0) { self.hasDisc = 1; }
     }
 
-    // ---------- FIFO ops ---------------------------------------------
+    // FIFO ops
     // Two separate FIFOs (param / resp) — methods are duplicated rather
     // than parameterized to keep the index/buffer pairing type-safe.
     // Same ring-buffer math the old `qPush`/`qPop` did, just with
@@ -246,7 +246,7 @@ pub const Cdrom = struct {
         self.respW = 0;
     }
 
-    // ---------- status byte ------------------------------------------
+    // status byte
 
     // Mirrors psxe cdrom_get_stat (cdrom.c:454): SPINDLE always, plus
     // READ while the sector pump is active, SHELLOPEN if no disc,
@@ -259,7 +259,7 @@ pub const Cdrom = struct {
         return s;
     }
 
-    // ---------- register I/O -----------------------------------------
+    // register I/O
 
     // Status register at offset 0 (always, regardless of bank).
     pub fn readStatus(self: mut Self) u32 {
@@ -359,7 +359,7 @@ pub const Cdrom = struct {
         self.write8(off + 3, (val >> 24) & 0xFF);
     }
 
-    // ---------- state-machine tick -----------------------------------
+    // state-machine tick
 
     // Handle the command response — equivalent to psxe's
     // `cdrom_cmd_table[cmd](cdrom)` running after the TX_RESP1 delay.
@@ -1043,7 +1043,7 @@ pub const Cdrom = struct {
     }
 };
 
-// ---------- free helpers (no state required) -----------------------
+// free helpers (no state required)
 
 // Binary-to-BCD encoder (psxe ITOB). Inputs 0..99.
 pub fn bcdEnc(v: u32) u32 {
diff --git a/cpu.jam b/cpu.jam
index bae3ed8..7d0c3a7 100644
--- a/cpu.jam
+++ b/cpu.jam
@@ -89,7 +89,7 @@ const CAUSE_RI:      u32 = 0x28;
 const CAUSE_CPU:     u32 = 0x2C;
 const CAUSE_OV:      u32 = 0x30;
 
-// ---------- register file ----------------------------------------------
+// register file
 //
 // 32 GPRs + 16 COP0 registers — both live in heap-allocated `Vec(u32)`
 // buffers that auto-drop with their owning scope. Callers pass `regs.ptr`
@@ -126,7 +126,7 @@ pub fn freshCpuAt(pc: u32) Cpu {
     return c;
 }
 
-// ---------- sign-extension and signed compare helpers ------------------
+// sign-extension and signed compare helpers
 
 pub fn signExt16(v: u32) u32 {
     if ((v & 0x8000) != 0) { return v | 0xFFFF0000; }
@@ -150,7 +150,7 @@ pub fn signedGtZero(a: u32) bool { return a != 0 && (a & 0x80000000) == 0; }
 pub fn signedLeZero(a: u32) bool { return a == 0 ||  (a & 0x80000000) != 0; }
 pub fn signedGeZero(a: u32) bool { return (a & 0x80000000) == 0; }
 
-// ---------- integer division -------------------------------------------
+// integer division
 //
 // MIPS DIV / DIVU semantics: division by zero produces -1 (signed) or
 // 0xFFFFFFFF (unsigned) for the quotient; signed INT_MIN / -1 stays at
@@ -189,7 +189,7 @@ pub fn modI32(a: u32, b: u32) u32 {
     return ((a as i32) % (b as i32)) as u32;
 }
 
-// ---------- exception machinery ----------------------------------------
+// exception machinery
 
 pub fn raiseException(c: mut Cpu, cop0: *mut[] u32, cause: u32) {
     var sr: u32 = cop0Read(cop0, C0_SR);
@@ -222,7 +222,7 @@ pub fn cop0Rfe(cop0: *mut[] u32) {
     cop0Write(cop0, C0_SR, sr);
 }
 
-// ---------- instruction-field accessors --------------------------------
+// instruction-field accessors
 
 pub fn opPrim(opc: u32) u32 { return (opc >> 26) & 0x3F; }
 pub fn opRs  (opc: u32) u32 { return (opc >> 21) & 0x1F; }
@@ -250,7 +250,7 @@ pub fn commitLoad(c: mut Cpu, regs: *mut[] u32) {
     c.loadV = 0;
 }
 
-// ---------- instruction implementations --------------------------------
+// instruction implementations
 
 pub fn iLui(c: mut Cpu, opc: u32, regs: *mut[] u32) {
     commitLoad(c, regs);
@@ -312,7 +312,7 @@ pub fn iSltiu(c: mut Cpu, opc: u32, regs: *mut[] u32) {
     gprWrite(regs, opRt(opc), v);
 }
 
-// --- branches ---
+// branches
 
 pub fn iJ(c: mut Cpu, opc: u32, regs: *mut[] u32) {
     commitLoad(c, regs);
@@ -388,7 +388,7 @@ pub fn iRegimm(c: mut Cpu, opc: u32, regs: *mut[] u32) {
     if (take) { doBranch(c, opImmS(opc) << 2); }
 }
 
-// --- loads ---
+// loads
 
 pub fn iLb(c: mut Cpu, opc: u32, bus: Bus, regs: *mut[] u32) {
     const s: u32 = gprRead(regs, opRs(opc));
@@ -475,7 +475,7 @@ pub fn iLwr(c: mut Cpu, opc: u32, bus: Bus, regs: *mut[] u32) {
     c.loadV = value;
 }
 
-// --- stores ---
+// stores
 
 pub fn iSb(c: mut Cpu, opc: u32, bus: Bus, regs: *mut[] u32, cop0: *mut[] u32) {
     const s: u32 = gprRead(regs, opRs(opc));
@@ -545,7 +545,7 @@ pub fn iSwr(c: mut Cpu, opc: u32, bus: Bus, regs: *mut[] u32, cop0: *mut[] u32)
     busWrite32(bus, cop0, aligned, v);
 }
 
-// --- SPECIAL family ---
+// SPECIAL family
 
 pub fn iSll(c: mut Cpu, opc: u32, regs: *mut[] u32) {
     const t: u32 = gprRead(regs, opRt(opc));
@@ -793,7 +793,7 @@ pub fn iSltu(c: mut Cpu, opc: u32, regs: *mut[] u32) {
     gprWrite(regs, opRd(opc), v);
 }
 
-// --- COP0 ---
+// COP0
 
 pub fn iMfc0(c: mut Cpu, opc: u32, regs: *mut[] u32, cop0: *mut[] u32) {
     const v: u32 = cop0Read(cop0, opRd(opc));
@@ -922,7 +922,7 @@ pub fn illegal(c: mut Cpu, opc: u32, regs: *mut[] u32, cop0: *mut[] u32) {
     raiseException(c, cop0, CAUSE_RI);
 }
 
-// ---------- decode + dispatch ------------------------------------------
+// decode + dispatch
 
 pub fn dispatchSpecial(c: mut Cpu, opc: u32, bus: Bus,
                       regs: *mut[] u32, cop0: *mut[] u32) {
@@ -1242,7 +1242,7 @@ pub fn run(c: mut Cpu, bus: Bus, regs: *mut[] u32, cop0: *mut[] u32,
     commitLoad(c, regs);
 }
 
-// ---------- BIOS A/B-table hooks ---------------------------------------
+// BIOS A/B-table hooks
 
 // Emit one BIOS console byte. std/fmt.print's `{b}` interpolation on a
 // `[]u8` slice dispatches to a raw byte-write (same `@emitWriteBytes`
@@ -1307,7 +1307,7 @@ pub fn runHooked(c: mut Cpu, bus: Bus, regs: *mut[] u32, cop0: *mut[] u32,
     commitLoad(c, regs);
 }
 
-// ---------- MIPS instruction encoders (for hand-assembling tests) ------
+// MIPS instruction encoders (for hand-assembling tests)
 
 pub fn encR(op: u32, rs: u32, rt: u32, rd: u32, sa: u32, fn_: u32) u32 {
     return ((op  & 0x3F) << 26)
diff --git a/cue.jam b/cue.jam
index 3e9c86a..889ac7a 100644
--- a/cue.jam
+++ b/cue.jam
@@ -96,7 +96,7 @@ pub const Cue = struct {
     }
 };
 
-// ---------- helpers ----------------------------------------------------
+// helpers
 
 pub fn isAlpha(c: u32) bool {
     if (c >= 0x41 && c <= 0x5A) { return true; }
@@ -202,7 +202,7 @@ pub fn kwId(buf: *mut[] u8) u32 {
     return 0;
 }
 
-// ---------- allocator -------------------------------------------------
+// allocator
 
 // Allocate a Box(Cue) with each inner Vec sized to its MAX_/cap. The
 // Vecs are filled-with-zero so the existing index-based writes by
@@ -271,7 +271,7 @@ pub fn pathBufAppend(raw: *mut[] u8, src: *mut[] u8, len: u32) u32 {
     return off;
 }
 
-// ---------- track-range computation -----------------------------------
+// track-range computation
 //
 // After parsing all FILE/TRACK/INDEX lines, walk each file's track list
 // and compute startLba/endLba. Mirrors psxe init_tracks().
@@ -335,7 +335,7 @@ pub fn cueComputeRanges(raw: *mut[] u8) {
     }
 }
 
-// ---------- lookup helpers --------------------------------------------
+// lookup helpers
 
 pub fn cueGetTrackCount(raw: *mut[] u8) u32 {
     var c: *mut[] Cue = raw as *mut[] Cue;
@@ -430,7 +430,7 @@ pub fn cueQuery(raw: *mut[] u8, lba: u32) u32 {
     return 0;
 }
 
-// ---------- parser ----------------------------------------------------
+// parser
 //
 // Stream the .cue text char-by-char (psxe's fgetc model). Each keyword
 // dispatches to its handler; FILE pushes onto files[], TRACK pushes
diff --git a/disc.jam b/disc.jam
index 6c1edcd..8740249 100644
--- a/disc.jam
+++ b/disc.jam
@@ -162,7 +162,7 @@ pub fn discLoaded(d: *mut[] Disc) i32 {
     return 1;
 }
 
-// ---- track info (for CDROM GetTN/GetTD/GetLocP/seek) -------------------
+// track info (for CDROM GetTN/GetTD/GetLocP/seek)
 // Route to the cue track table when cue-loaded; a raw .bin is a single
 // Mode2/2352 data track starting at the lead-in (LBA 150).
 
diff --git a/dma.jam b/dma.jam
index 7778f53..bd2a5ff 100644
--- a/dma.jam
+++ b/dma.jam
@@ -58,7 +58,7 @@ pub fn dmaAlloc() Vec(u32) {
 
 pub fn chBase(ch: u32) u32 { return ch * 3; }
 
-// ---------- direct RAM access (DMA never targets BIOS/scratchpad) -------
+// direct RAM access (DMA never targets BIOS/scratchpad)
 //
 // The DMA controller bypasses the bus's address-space mapping when
 // reading sources or writing destinations — addresses in the channel
@@ -90,7 +90,7 @@ pub fn ramWrite16(bus: Bus, addr: u32, val: u32) {
     p[off + 1] = ((val >> 8) & 0xFF) as u8;
 }
 
-// ---------- IO surface --------------------------------------------------
+// IO surface
 
 // Per-channel CHCR hardwiring masks (psxe dma.c lines 14-24). Channels
 // 0..5 expose the full 32-bit CHCR through these mask bits; channel 6
@@ -253,7 +253,7 @@ pub fn dmaClear(d: *mut[] u32, ch: u32) {
     d[chBase(ch) + F_BCR]  = 0;
 }
 
-// --- per-channel transfer routines ---
+// per-channel transfer routines
 
 pub fn dmaDoGpu(d: *mut[] u32, bus: Bus) {
     if (!chcrBusy(d, 2)) { return; }
diff --git a/gpu.jam b/gpu.jam
index 3e8e91a..7cfa0e7 100644
--- a/gpu.jam
+++ b/gpu.jam
@@ -92,7 +92,7 @@ pub fn vramReadPixel(vram: *mut[] u8, x: u32, y: u32) u32 {
     return (vram[off] as u32) | ((vram[off + 1] as u32) << 8);
 }
 
-// ---------- GP0 / GP1 reads --------------------------------------------
+// GP0 / GP1 reads
 
 pub fn gpuRead32(g: *mut[] u32, vram: *mut[] u8, off: u32) u32 {
     if (off == 0x00) {
@@ -157,7 +157,7 @@ pub fn vramPackTwo(g: *mut[] u32, vram: *mut[] u8) u32 {
     return data;
 }
 
-// ---------- GP0 (command/data) writes ----------------------------------
+// GP0 (command/data) writes
 
 pub fn gpuWrite32(g: *mut[] u32, vram: *mut[] u8, off: u32, val: u32) {
     match (off) {
@@ -472,7 +472,7 @@ pub fn gpuVramToCpu(g: *mut[] u32, vram: *mut[] u8) {
     g[19] = GP_RECV_CMD;
 }
 
-// --- polygon / line / rect command parsing ---
+// polygon / line / rect command parsing
 //
 // We parse the variant flags (textured, gouraud, 4-vert) to compute the
 // right argument count, latch all the args, then stub the rasterization
@@ -1349,7 +1349,7 @@ pub fn gpuBlend(fore: u32, back: u32, mode: u32) u32 {
     return gpuToBgr555(cr | (cg << 8) | (cb << 16));
 }
 
-// ---------- frame pacing -----------------------------------------------
+// frame pacing
 //
 // Each call advances the GPU's scanline cycle counter. When we cross a
 // horizontal-draw / hblank boundary we tick `line`; at scanline 240 we
@@ -1365,7 +1365,7 @@ const GPU_CYC_SCANL_NTSC: u32 = 3413;
 const GPU_LINES_VDRAW:    u32 = 240;
 const GPU_LINES_TOTAL:    u32 = 263;
 
-// ---------- struct wrapper -------------------------------------------
+// struct wrapper
 //
 // `Gpu` owns the 80-u32 state buffer inline (vs the old heap alloc)
 // and exposes the public surface as methods. The internal command-
diff --git a/gte.jam b/gte.jam
index 4fe9485..b5a3588 100644
--- a/gte.jam
+++ b/gte.jam
@@ -694,7 +694,7 @@ pub fn satIrLm(v: i64, lm: u32) i64 {
     return v;
 }
 
-// ---- FLAG-aware clamps (psxe gte_clamp_* / gte_check_mac, cpu.c:1486-1607)
+// FLAG-aware clamps (psxe gte_clamp_* / gte_check_mac, cpu.c:1486-1607)
 // Each ORs the matching FLAG bit into g[32+C_FLAG] on saturation/overflow
 // and otherwise returns exactly what the plain sat* helpers return, so
 // MAC/IR/SXY/RGB *values* are unchanged — only FLAG gets populated. `i`
diff --git a/main.jam b/main.jam
index 823cc70..97fa995 100644
--- a/main.jam
+++ b/main.jam
@@ -342,7 +342,7 @@ fn runOneFrame(c: mut Cpu, bus: Bus, regs: *mut[] u32, cop0: *mut[] u32,
         dmaTickSpu(bus.dma.ptr, delta);
         dmaUpdate(bus.dma.ptr, bus.irq.ptr, cop0);
 
-        // --- jam-only extras: psxe steps NEITHER in psx_update. Kept at the
+        // jam-only extras: psxe steps NEITHER in psx_update. Kept at the
         // end (least perturbation to the psxe device order above) and flagged
         // as divergences — SIO1 → peripherals task, SPU CPU-clock → SPU task
         // (psxe runs SPU on the audio thread; revisit once the deterministic
@@ -427,7 +427,7 @@ fn dumpVramPpm(path: []u8, vram: *mut[] u8) {
     }
 }
 
-// ---------- main --------------------------------------------------------
+// main
 
 // True if NUL-terminated `p` ends with ".exe" / ".EXE". Mirrors
 // disc.jam's pathEndsWithCue so an EXE passed as argv[2] is routed to
diff --git a/mdec.jam b/mdec.jam
index ef77ade..dc77536 100644
--- a/mdec.jam
+++ b/mdec.jam
@@ -129,7 +129,7 @@ pub const Mdec = struct {
         };
     }
 
-    // ---------- iDCT (mdec.c:45 real_idct) ----------------------------
+    // iDCT (mdec.c:45 real_idct)
     //
     // Two-pass 8×8 transform. The block (blk) provides both the input
     // and final output; we ping-pong through the scratch slot at
@@ -142,7 +142,7 @@ pub const Mdec = struct {
         // final result lives in blk[0..64].
     }
 
-    // ---------- RLE block decode (mdec.c:72 rl_decode_block) ---------
+    // RLE block decode (mdec.c:72 rl_decode_block)
     //
     // Reads 16-bit words from `input` starting at `inIdx`. Decodes one
     // block into `blk` (a 128-entry i16 array; lower 64 are the live
@@ -195,7 +195,7 @@ pub const Mdec = struct {
         return idx;
     }
 
-    // ---------- YUV → RGB (mdec.c:135 yuv_to_rgb) ---------------------
+    // YUV → RGB (mdec.c:135 yuv_to_rgb)
     pub fn yuvToRgb(self: mut Self, output: *mut[] u8, outBase: u32,
                     xx: u32, yy: u32) {
         const depth: u32 = self.outputDepth;
@@ -253,7 +253,7 @@ pub const Mdec = struct {
         }
     }
 
-    // ---------- decode macroblock (mdec.c:180) ------------------------
+    // decode macroblock (mdec.c:180)
     pub fn decodeMacroblock(self: mut Self,
                             input: *mut[] u8, output: *mut[] u8) {
         const depth: u32 = self.outputDepth;
@@ -315,7 +315,7 @@ pub const Mdec = struct {
         self.outputIndex = 0;
     }
 
-    // ---------- command dispatch (write to 0x1F801820) ---------------
+    // command dispatch (write to 0x1F801820)
     pub fn setQt(self: mut Self, input: *mut[] u8) {
         var i: u32 = 0;
         while (i < 64) {
@@ -362,7 +362,7 @@ pub const Mdec = struct {
         }
     }
 
-    // ---------- bus dispatch (mdec.c:287/348) ------------------------
+    // bus dispatch (mdec.c:287/348)
     pub fn read32(self: mut Self, output: *mut[] u8, off: u32) u32 {
         if (off == 0) {
             // Data port — drain one word from the output buffer.
@@ -522,13 +522,13 @@ pub const Mdec = struct {
     }
 };
 
-// ---------- input/output buffer allocation (still heap-resident) -----
+// input/output buffer allocation (still heap-resident)
 
 // Owned MDEC IO buffers. Auto-drop with the Bus.
 pub fn mdecInputAlloc()  Vec(u8) { return Vec(u8).filled(0, MDEC_INPUT_SIZE); }
 pub fn mdecOutputAlloc() Vec(u8) { return Vec(u8).filled(0, MDEC_OUTPUT_SIZE); }
 
-// ---------- free helpers (no state required) -------------------------
+// free helpers (no state required)
 
 pub fn exts10(v: u32) i32 {
     const t: u32 = (v << 22) & 0xFFFFFFFF;
diff --git a/pad.jam b/pad.jam
index 1b92596..5bd8eb0 100644
--- a/pad.jam
+++ b/pad.jam
@@ -263,7 +263,7 @@ pub fn padReadStat(p: *mut[] u8) u32 {
     return padGetU16(p, P_STAT_LO) | 0x07;
 }
 
-// ---------- public IO surface ------------------------------------------
+// public IO surface
 
 pub fn padRead32(p: *mut[] u8, mcd: mut Mcd, mcdRam: *mut[] u8, off: u32) u32 {
     match (off) {
diff --git a/sdl.jam b/sdl.jam
index 28c0307..d27f565 100644
--- a/sdl.jam
+++ b/sdl.jam
@@ -65,7 +65,7 @@ extern fn SDL_Delay(ms: u32);
 extern fn SDL_PollEvent(event: *mut[] u8) i32;
 extern fn SDL_GetTicks() u32;
 
-// --- macOS App Nap disable (Objective-C runtime) ---
+// macOS App Nap disable (Objective-C runtime)
 // When the jam window is not focused, macOS App Nap throttles the process's
 // timers + CPU, stalling the single-threaded emulation loop ("stuck when not
 // focused"). Disable it by holding a user-initiated NSProcessInfo activity.
@@ -76,7 +76,7 @@ extern fn objc_getClass(name: *const[] u8) u64;
 extern fn sel_registerName(name: *const[] u8) u64;
 extern fn objc_msgSend(recv: u64, sel: u64, a: u64, b: u64) u64;
 
-// --- audio ---
+// audio
 //
 // Callback-mode SDL audio with an SPSC ring buffer. The SPU is NOT
 // driven by the audio thread (it's clocked CPU-synchronously inside
@@ -280,7 +280,7 @@ pub fn sdlAudioClose(dev: u32) {
     if (dev != 0) { SDL_CloseAudioDevice(dev); }
 }
 
-// ---- SPSC audio ring buffer ---------------------------------------
+// SPSC audio ring buffer
 // The CPU loop (producer) pushes the per-frame sample batch; SDL's
 // audio callback (consumer) drains it at the host rate. Layout of the
 // `userdata` blob handed to SDL (indices are byte offsets into the
diff --git a/sio1.jam b/sio1.jam
index fe89417..d95011b 100644
--- a/sio1.jam
+++ b/sio1.jam
@@ -118,7 +118,7 @@ pub const Sio1 = struct {
         return b;
     }
 
-    pub fn rxEmpty(self: mut Self) bool {
+    pub fn rxEmpty(self: Self) bool {
         return self.rxHead == self.rxTail;
     }
 
@@ -126,7 +126,7 @@ pub const Sio1 = struct {
     // read we OR in the dynamic bits — TX_RDY1 always 1 (FIFO never
     // full since we transmit immediately), TX_RDY2 = 1 when no TX in
     // flight, RX_NE = 1 when RX FIFO has data.
-    pub fn readStat(self: mut Self) u32 {
+    pub fn readStat(self: Self) u32 {
         var stat: u32 = self.stat;
         stat = stat | STAT_TXR1;
         if (self.txPending == 0) { stat = stat | STAT_TXR2; }
diff --git a/spu.jam b/spu.jam
index 7ca24a6..8458e61 100644
--- a/spu.jam
+++ b/spu.jam
@@ -208,7 +208,7 @@ pub fn adpcmNeg(f: u32) i32 {
     }
 }
 
-// ---------- noise generator (Avocado/DuckStation/nocash) ---------------
+// noise generator (Avocado/DuckStation/nocash)
 //
 // SPUCNT bits 8-13 are the noise clock: shift = bits 10-13, step = bits 8-9.
 // noiseFreqAdd is the {0,84,140,180,210} half-cycle table (index 4 = 210 is
@@ -251,7 +251,7 @@ fn spuStepNoise(s: *mut[] u8, spucnt: u32) {
     setU32(s, GLOBAL_BASE + G_NOISE_COUNT, count);
 }
 
-// ---------- allocation -------------------------------------------------
+// allocation
 
 // Owned SPU-state buffer (~29KB). Initialised via setU16 + spuGaussInit
 // (psxe's reset values: all voices ended, irq9addr = 0xFFFF). Auto-drops
@@ -270,7 +270,7 @@ pub fn spuAlloc() Vec(u8) {
 // with the Bus.
 pub fn spuRamAlloc() Vec(u8) { return Vec(u8).filled(0, SPU_RAM_SIZE); }
 
-// ---------- CD-audio FIFO ---------------------------------------------
+// CD-audio FIFO
 //
 // XA samples decoded by cdrom.jam land here as packed (left, right) i16
 // pairs. spuGetSample drains one entry per call and adds it (volume-
@@ -288,7 +288,7 @@ pub fn spuPushCdSample(s: *mut[] u8, leftI16: u32, rightI16: u32) {
     setU32(s, GLOBAL_BASE + G_CD_HEAD, head + 1);
 }
 
-// ---------- reverb -----------------------------------------------------
+// reverb
 //
 // PSX reverb is a 22-tap filter living in the tail of SPU RAM starting
 // at MBASE×8. The work-area is referenced through a rotating cursor
@@ -467,7 +467,7 @@ pub fn spuPopCdSample(s: *mut[] u8) u32 {
     return l | (r << 16);
 }
 
-// ---------- byte-buffer access helpers --------------------------------
+// byte-buffer access helpers
 
 pub fn getU16(s: *mut[] u8, off: u32) u32 {
     return (s[off] as u32) | ((s[off + 1] as u32) << 8);
@@ -553,7 +553,7 @@ pub fn clamp7fff(v: i32) i32 {
 }
 pub fn maxI(a: i32, b: i32) i32 { if (a > b) { return a; } return b; }
 
-// ---------- ADPCM block decoder (psxe spu_read_block) ----------------
+// ADPCM block decoder (psxe spu_read_block)
 
 pub fn spuReadBlock(s: *mut[] u8, ram: *mut[] u8, v: u32) {
     const base: u32 = voiceRTBase(v);
@@ -594,7 +594,7 @@ pub fn spuReadBlock(s: *mut[] u8, ram: *mut[] u8, v: u32) {
     setI32(s, base + D_H1, h1);
 }
 
-// ---------- ADSR ------------------------------------------------------
+// ADSR
 
 pub fn adsrCalcValues(s: *mut[] u8, v: u32) {
     const base: u32 = voiceRTBase(v);
@@ -723,7 +723,7 @@ pub fn spuStepAdsrCpu(s: *mut[] u8) {
     }
 }
 
-// ---------- KON / KOFF -----------------------------------------------
+// KON / KOFF
 
 pub fn spuKon(s: *mut[] u8, ram: *mut[] u8, value: u32) {
     var i: u32 = 0;
@@ -764,7 +764,7 @@ pub fn spuKoff(s: *mut[] u8, value: u32) {
     }
 }
 
-// ---------- write-side effects (psxe spu_handle_write) ----------------
+// write-side effects (psxe spu_handle_write)
 
 pub fn spuHandleWrite(s: *mut[] u8, ram: *mut[] u8, off: u32, val: u32) i32 {
     if (off == R_KONL || off == R_KONH) {
@@ -842,7 +842,7 @@ pub fn spuHandleWrite(s: *mut[] u8, ram: *mut[] u8, off: u32, val: u32) i32 {
     return 0;
 }
 
-// ---------- read TFIFO (psxe spu_read16 SPUR_TFIFO branch) ------------
+// read TFIFO (psxe spu_read16 SPUR_TFIFO branch)
 
 pub fn spuReadTfifo(s: *mut[] u8, ram: *mut[] u8) u32 {
     var ta: u32 = getU32(s, GLOBAL_BASE + G_TADDR);
@@ -852,7 +852,7 @@ pub fn spuReadTfifo(s: *mut[] u8, ram: *mut[] u8) u32 {
     return lo | (hi << 8);
 }
 
-// ---------- bus dispatch ---------------------------------------------
+// bus dispatch
 
 pub fn spuRead8(s: *mut[] u8, ram: *mut[] u8, off: u32) u32 {
     if (off >= SPU_REG_SIZE) { return 0; }
@@ -893,7 +893,7 @@ pub fn spuWrite32(s: *mut[] u8, ram: *mut[] u8, off: u32, val: u32) {
     setU16(s, off + 2, (val >> 16) & 0xFFFF);
 }
 
-// ---------- sample mixer (psxe psx_spu_get_sample) --------------------
+// sample mixer (psxe psx_spu_get_sample)
 
 pub fn spuGetSample(s: *mut[] u8, ram: *mut[] u8,
                     ic: *mut[] u32, cop0: *mut[] u32) u32 {
@@ -1132,7 +1132,7 @@ pub fn spuOutAvailable(s: *mut[] u8) u32 {
          - getU32(s, GLOBAL_BASE + G_OUT_TAIL);
 }
 
-// ---------- per-scanline tick ----------------------------------------
+// per-scanline tick
 //
 // PS1 CPU is 33.8688 MHz, SPU runs at 44.1 kHz, so 1 sample ≈ 768 CPU
 // cycles. We accumulate cycles and drain one spuGetSample per bucket.
@@ -1153,7 +1153,7 @@ pub fn spuUpdate(s: *mut[] u8, ram: *mut[] u8,
     setU32(s, GLOBAL_BASE + G_SAMPLE_ACC, acc);
 }
 
-// ---------- Gaussian interpolation ------------------------------------
+// Gaussian interpolation
 //
 // Replaces the previous nearest-neighbor sample lookup with the 4-tap
 // Gaussian filter PSX hardware uses. Lookup table lives at offset
diff --git a/tests.jam b/tests.jam
index 67f7071..ade84ad 100644
--- a/tests.jam
+++ b/tests.jam
@@ -361,7 +361,7 @@ tfn psxSyscallVector()  { assert(tSyscallVector(), 0xBFC00180); }
 tfn psxLoadDelay()      { assert(tLoadDelay(), 0x0000002A); }
 tfn psxLwlLwr()         { assert(tLwlLwr(), 0xBBCCDD11); }
 
-// ---------- GTE (COP2) unit tests ----------------------------------------
+// GTE (COP2) unit tests
 //
 // gteAlloc gives a standalone register buffer, so the math ops can be
 // exercised without a full Bus. These lock in the psxe-match fixes:
@@ -565,7 +565,7 @@ tfn psxGteRtptDqGate() { assert(tGteRtptDqGate(), 0); }
 tfn psxGteNcdsRgbSat() { assert(tGteNcdsRgbSat(), 0x00200000); }
 tfn psxGteDqaWidth()   { assert(tGteDqaWidth(), 16); }
 
-// ---------- headless emulator boot tests ---------------------------------
+// headless emulator boot tests
 //
 // These tests boot the real BIOS (and optionally a disc image) into a
 // fully-allocated Bus without SDL, then run N frames and assert state.
@@ -692,7 +692,7 @@ tfn emuDiscBootsExec() {
 // pushes an INT3/INT2/INT5 response, so a non-zero value proves the CD
 // state machine got exercised.
 
-// ---- variable per-instruction cycle model (psxe cpu.c last_cycles) -----
+// variable per-instruction cycle model (psxe cpu.c last_cycles)
 //
 // step() charges `fetchCyc + instrCyc` per instruction, matching psxe:
 // fetchCyc = 18 when the opcode is read from BIOS ROM (bios.c bus_delay)