const std = @import("std");
const zesty = @import("../zesty.zig");
const assembler = @import("cpu/assembler.zig");

pub const assemble = assembler.assembleComptime;

test {
    _ = assembler;
    _ = @import("cpu/addressing.zig");
    _ = @import("cpu/alu.zig");
    _ = @import("cpu/control_flow.zig");
    _ = @import("cpu/stack.zig");
    _ = @import("cpu/undocumented.zig");
}

//------------------------------------------------------
// Test harnesses

pub const TestInit = struct {
    /// NMI vector
    nmi: u16 = 0x8000,
    /// RESET vector
    reset: u16 = 0x8000,
    /// IRQ/BRK vector
    irq: u16 = 0x8000,

    /// Pre-run the reset sequence
    init_cpu: bool = true,

    ram: []const struct { u16, []const u8 } = &.{},
    rom: []const struct { u16, []const u8 } = &.{},
};

pub fn testZes(opts: TestInit) zesty.Zesty {
    var cart: zesty.cartridge.Nrom128 = .{};

    // NMI vector
    @memmove(
        cart.rom[0xfffa & 0x3fff ..][0..2],
        &std.mem.toBytes(std.mem.nativeToLittle(u16, opts.nmi)),
    );
    // RESET vector
    @memmove(
        cart.rom[0xfffc & 0x3fff ..][0..2],
        &std.mem.toBytes(std.mem.nativeToLittle(u16, opts.reset)),
    );
    // IRQ vector
    @memmove(
        cart.rom[0xfffe & 0x3fff ..][0..2],
        &std.mem.toBytes(std.mem.nativeToLittle(u16, opts.irq)),
    );

    for (opts.rom) |v| {
        const offset, const bytes = v;
        @memmove(cart.rom[offset & 0x3fff ..][0..bytes.len], bytes);
    }
    var z: zesty.Zesty = .init(.top_loader_ntsc);
    z.cart = .{ .nrom128 = cart };

    for (opts.ram) |v| {
        const offset, const bytes = v;
        @memmove(z.ram[offset & 0x7ff ..][0..bytes.len], bytes);
    }

    if (opts.init_cpu)
        while (!z.cpu.sync) z.stepCpu();

    return z;
}

pub fn run(z: *zesty.Zesty) void {
    z.stepCpu();
    while (!z.cpu.sync) z.stepCpu();
}

pub fn runDebug(z: *zesty.Zesty) void {
    z.stepCpu();
    debug(z);
    while (!z.cpu.sync) {
        z.stepCpu();
        debug(z);
    }
}

pub fn debug(z: *zesty.Zesty) void {
    std.debug.print(
        "#{} addr:{X:04} data:{X:02} {c} pc:{X:04} a:{X:02} x:{X:02} y:{X:02} sp:{X:02} ir:{X:02} {f}\n",
        .{
            z.cpu.cycle -| 1,
            z.pins.cpu_addr,
            z.pins.cpu_data,
            @as(u8, if (z.pins.cpu_rw == .read) 'r' else 'w'),
            z.cpu.pc,
            z.cpu.a,
            z.cpu.x,
            z.cpu.y,
            z.cpu.sp,
            z.cpu.opcode,
            z.cpu.status,
        },
    );
}