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or1-design
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OR-1 dataflow CPU sketch
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Overview
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or1-design
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docs
4 folders
·
4 files
at commit
5e7116ea
Orual
·
feat: add Instruction, OutputStyle, FrameDest, TokenKind, FrameOp; renumber all opcodes to 5-bit hardware encoding; remove ALUInst, SMInst, Addr, FREE_CTX
·
7mo ago
8960e6b7
design-plans
docs: add unified PE frame-based redesign design plan
7mo ago
implementation-plans
feat: add Instruction, OutputStyle, FrameDest, TokenKind, FrameOp; renumber all opcodes to 5-bit hardware encoding; remove ALUInst, SMInst, Addr, FREE_CTX
7mo ago
plans
bugfixes in monitor and graph renderer, improvements to SM visibility
7mo ago
test-plans
feat(asm): implement macro system, function calls, and ${param} substitution
7mo ago
assembler-redesign-plan.md
docs: add unified PE frame-based redesign design plan
7mo ago
emulator-redesign-plan.md
docs: add unified PE frame-based redesign design plan
7mo ago
macro-enhancements.md
updating docs
7mo ago
test-requirements.md
fix(asm): address code review issues — invalid port errors, @ret leak, test gaps
7mo ago
