diff --git a/README.md b/README.md
index 908332a..6f0daf6 100644
--- a/README.md
+++ b/README.md
@@ -3,6 +3,7 @@ A simple single-cycle RV32IZicsr core written in AmaranthHDL. Designed to be rea
 
 Still WIP.
 
+TODO: This file
 ### Planned Features
 - Base I extension
 - Zicsr extension
diff --git a/buses.py b/buses.py
index cb56f8a..9e4cdae 100644
--- a/buses.py
+++ b/buses.py
@@ -5,6 +5,7 @@ from amaranth.lib import wiring
 from amaranth.lib.wiring import In, Out
 
 
+# NOTE: Small bus until base RV32I is verified to work
 class PicoBus(wiring.Signature):
     def __init__(self):
         super().__init__({
@@ -20,6 +21,7 @@ class PicoBus(wiring.Signature):
         })
 
 
+# TODO: To be used later
 class AXILite(wiring.Signature):
     def __init__(self, address_width, data_width):
         assert address_width % 8 == 0,  "Address width must be divisible by 8"
diff --git a/cpu.py b/cpu.py
index 1b87d88..f5f42f7 100644
--- a/cpu.py
+++ b/cpu.py
@@ -26,6 +26,7 @@ class CPU(wiring.Component):
     def __init__(self):
         super().__init__()
 
+    # TODO: Do prefetch
     def instr_fetch(self, m, PC):
         m.d.comb += [
             self.bus.mem_valid.eq(1),
@@ -33,6 +34,7 @@ class CPU(wiring.Component):
             self.bus.mem_addr .eq(PC)
         ]
 
+    # TODO: Set bus signals to minimize wait states
     def mem_load(self, m, mem_addr):
         m.d.comb += [
             self.bus.mem_valid.eq(1),
@@ -50,6 +52,7 @@ class CPU(wiring.Component):
     def elaborate(self, platform):
         m = Module()
 
+        # TODO: Proper debug signals
         m.submodules.alu     = alu                      = ALU()
         m.submodules.decoder = self.decoder = decoder   = Decoder()
         m.submodules.regfile = self.regfile = regfile   = RegisterFile()
diff --git a/memory.py b/memory.py
index 4bf0d30..269d4dd 100644
--- a/memory.py
+++ b/memory.py
@@ -41,7 +41,8 @@ class SimpleROM(wiring.Component):
 
         return m
 
-
+# NOTE: This implementation might not be the best
+# however, It responds in a single cycle
 class SimpleRAM(wiring.Component):
     bus: In(PicoBus())
 
@@ -54,6 +55,7 @@ class SimpleRAM(wiring.Component):
     def elaborate(self, platform):
         m = Module()
 
+        # TODO: Proper debug signals
         m.submodules.ram = self.ram = ram = Memory(shape=32, depth=self.ram_size, init=self.ram_init)
         read_port   = ram.read_port()
         write_port  = ram.write_port(granularity=8)
diff --git a/regfile.py b/regfile.py
index 25a9009..0b2548a 100644
--- a/regfile.py
+++ b/regfile.py
@@ -27,6 +27,7 @@ class RegisterFile(wiring.Component):
     def elaborate(self, platform):
         m = Module()
 
+        # TODO: Proper debug signals
         m.submodules.memory = self.memory = memory = Memory(shape=32, depth=self.register_count, init=[], attrs={"ram_style":"distributed"})
         rd_port  = memory.write_port()
         rs1_port = memory.read_port(domain="comb")
diff --git a/top.py b/top.py
index 5e1b6c0..b32129b 100644
--- a/top.py
+++ b/top.py
@@ -1,5 +1,6 @@
 # pyright: reportInvalidTypeForm=false
 
+# TODO: Testing framework
 from amaranth import *
 from amaranth.lib import wiring
 from amaranth.sim import Simulator, Period, SimulatorContext